1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to manufacturing approaches used in forming openings during interconnect processing of integrated circuits and other devices.
2. Related Art
The semiconductor manufacturing process typically includes two major components, namely the Front-End-of-Line (FEOL), which includes the multilayer process of forming semiconductor devices (transistors, etc.) on a semiconductor substrate, and the Back-End-Of-Line (BEOL), which includes the metallization after the semiconductor devices have been formed. Like all electronic devices, semiconductor devices in a microchip, such as an integrated circuit (IC), need to be electronically connected through wiring. In an integrated circuit, such wiring is done through multilayer metallization on top of the multilayered semiconductor devices formed on the semiconductor substrate. The complexity of this wiring becomes appreciable as there may be hundreds of millions or more semiconductor devices (e.g., transistors in particular) formed on a single IC. Proper connection of these devices is accomplished by multilayer metallization. Each metallization layer consists of a grid of metal lines sandwiched between one or more dielectric layers for electrical integrity. Modern semiconductor manufacturing processes can involve multiple metallization layers.
As scaling of microelectronic devices approaches sub 30 nm nodes, many material and module process challenges in BEOL plasma patterning have been reported. One of the methods that has gained traction over recent years for enabling sub 20 nm feature patterning is the Trench First Metal Hard Mask (TFMHM) scheme. While this scheme solves or mitigates many challenges that are inherent with the Via First Trench Last (VFTL) Scheme, it introduced other dielectric reactive ion etching (RIE) process and hardware challenges. One of the root causes of the former is the fact that all patterns and materials are exposed to plasma at the same time. As such, the simultaneous control of via, trench and chamfer profiles (i.e. Critical Dimensions, depth, taper profile, etc), the need to control selectivity between multiple patterning layer (Titanium Nitride (TiN), tetra-ethyl-ortho-silane (TEOS), ultra low k (ULK), Barrier cap, etc), and ULK damage control has become more pertinent in the dielectric etch. As a direct result of such tight process guidelines, the hardware challenges arise and new dimensions in process controls are needed. The prolonged exposure of the TiN to the plasma created the need for more robust production worthy hardware. The required selectivity of the materials necessitate temperature controllable chucks. The more complex patterning techniques require ULK preservation and other uniformity controls.
A TFMHM Self-Alignment Via (SAV) process is used to improve the via to trench alignment margin in order to maximizes the Vx/Mx+1 spacing. Merged vias can help further reduce the via-to-via distance and thus improve the device density. Selectivity to the hardmask layer of an etch process, which is essential to enable the self-alignment, is challenging. The hardmask margin becomes worse when the merged via design is used since the hardmask is exposed to the etch process twice. The prior art device 10 of FIGS. 1-2 show this challenge. FIG. 1A (cross-sectional view) and FIG. 1B (top view) demonstrate a prior art device 10 including a substrate 2, a capping layer 4 (e.g., nitrogen-doped silicon carbide or SiNxCyHz(NBLoK)) formed over substrate 2, an interdielectric layer 6 formed over capping layer 4, a hard mask layer 8 (e.g., a TEOS hard mask layer), and a hard mask 14 formed over hard mask layer 8. Device 10 further comprises a plurality of vias 12 in a merged via region ‘R1’ following a via etch and strip process. As shown, ‘R2’ represents a non-merged region of device 10. FIGS. 2A-B represent device 10 of FIGS. 1A-B, respectively, following a trench etch. In this prior art approach, hard mask 14 (e.g. TiN) is exposed to the via etch and the subsequent trench etch, which forms vias 12 and a plurality of trenches 16. However, as demonstrated, an insufficient margin for hardmask 14 causes the hard mask 14 to break (highlighted by reference numeral 18 in FIG. 2A) during the merged via etch and the subsequent trench etch. This may result in a metal line to metal line short following metal chemical-mechanical polishing (CMP) in subsequent fabrication.
The hardmask loss in current art approaches occurs in two directions, vertically and horizontally. It is known the more robust the hardmask, the better protection for the material underneath the hardmask. On the other hand, process selectivity to the hardmask material can be improved by adjusting process parameters such as process chemistry and process temperature, etc. In order to improve the hardmask selectivity, the amount of polymering gas such as C4F8 is increased and the lower process temperature is used. However, the polymer residue risk becomes higher with increasing the C4F8 flow and lowering the process temperature. Physically increasing the hardmask thickness can provide better hardmask protection. However, it would result in too big an aspect ratio, which may cause a subsequent metal filling defect (e.g. void). Reducing the SAV etch time may help reduce the hardmask loss. However, the reduced SAV etch time causes the via open issue as a result of the under etch of dielectric material. As such, current art approaches are inadequate for at least one of the reasons described above.